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6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 1 rev 1 , may 2017 idtf 1912 n cg i datasheet g eneral d escription this document describes the specification for the idt f1912 digital step attenuator. the f1912 is part of a family of glitch - free tm dsas optimized for the demanding requirements of base station (bts) radio cards and numerous other non - bts applications. these devices are offered in a compact 4mm x 4mm 20 pin qfn package with 50 impedances for ease of integration. competitive advantag e digital step attenuators are used in receivers and transmitters to provide ga in control. the f1912 is a 6 - bit step attenuator optimized for these demanding applications. the silicon design has very low insertion loss and low distortion (> +60 dbm i ip3. ) the device has pinpoint accuracy. most importantly, the f1912 includes idts glitch - free tm technology which results in low overshoot & ringing during msb transitions . ? glitch - free tm technology so pa or adc will not be damaged during when transitions. ? ex tremely accurate with low distortion . ? lowest insertion loss for best snr applications ? base station 2g, 3g, 4g, tdd radio cards ? repeaters and e911 systems ? digital pre - distortion ? point to point infrastructure ? public safety infrastructure ? wimax receivers and transmitters ? military systems, jtrs radios ? rfid handheld and portable readers ? cable infrastructure o rdering i nformation f eatures ? serial & 6 bit parallel interface ? 31.5 db control range ? 0.5 db step ? glitch - free tm , low transient overshoot ? 3.0 v to 5.25 v supply ? 1.8 v or 3.3 v control logic ? attenuation error < 0.22 db @ 2 ghz ? low insertion loss < 1.6 db @ 2 ghz ? ultra linear iip3 >+59.5 dbm ? iip2 = +11 0 dbm typical ? stable integral non - linearity over temperature ? low current consumption 550 a typical ? - 40 c to +105 c operating temperature ? 4mm x 4mm thin qfn 20 pin package functiona l block diagram part# details part# freq range (mhz) resolution / range (db) control il (db) pinout f1950 150 - 4000 0.25 / 31.75 parallel & serial 1.3 pe 43702 pe43701 f195 1 100 - 4000 0. 50 / 31. 5 serial only 1.2 hmc305 f1952 100 C 4000 0.50 / 15.5 serial only 0.9 h mc305 f1953 400 C 4000 0.50 / 31 .5 parallel & serial 1.3 pe4302 dat - 31r5 f1956 1 - 4000 0.25 / 31.75 parallel & serial 1.4 pe43705, rfsa3715 f1912 1 C 4000 0.50 / 31.5 parallel & serial 1. 4 pe4312 pe4302 idt f1912ncg i8 0.8 mm height package green tape & reel omit idt prefix rf product line d e c o d e r r f 1 r f 2 d [ 5 : 0 ] s p i b i a s c l k d a t a l e v m o d e glitch - free tm glitch - free tm
6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 2 rev 1 , may 2017 idtf 1912 n cg i datasheet a bsolute m aximum r atings parameter symbol min max units v dd to gnd v dd - 0.3 +5.5 v data, le, clk, d[5:0] v logic - 0.3 min (v dd - 0.3, 3.6) v rf1, rf2 v rf - 0.3 +0.3 v maximum input power applied to rf1 or rf2 (>100 mhz) p rf +34 dbm o perating case temperature +105 c maximum junction temperature t jmax +14 0 c junction temperature t jmax 140 c continuous power dissipation 1.5 w storage temperature range t st - 65 150 c lead temperature (soldering, 10s) 260 c electrostatic discharge C hbm ( jedec/esda js - 001 - 2012 ) v esdhbm 20 00 ( class 2 ) volts esd voltage C cdm (per jesd22 - c101 f ) v esdcdm 500 ( class c2) volts stresses above those listed above may cause permanent damage to the device. functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. ex posure to absolute maximum rating conditions for extended periods may affect device reliability. esd c aution this product features proprietary protection circuitry. however, it may be damaged if subjected to high energy esd. please use proper esd precaut ions when handling to avoid damage or loss of performance. p ackage t hermal and m oisture c haracteristics ja (junction C ambient) 50 c/w jc (junction C case) [ the case is defined as the exposed paddle ] 3 c/w moisture sensitivity rating (per j - std - 020) msl1
6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 3 rev 1 , may 2017 idtf 1912 n cg i datasheet f1912 r ecommended o perating c onditions parameter symbol conditions min typ max units supply voltage(s) v dd 3 5.25 v freq uency range f rf 1 4000 mhz operating temperature range t case exposed paddle - 40 105 c rf cw input power pcw rf1 or rf2 see figure 1 dbm source impedance z source single ended 50 load impedance z load single ended 50 figure 1 maximum continuous operating rf input power v ersu s input f requency 0 4 8 12 16 20 24 28 32 0.01 0.10 1.00 10.00 100.00 1000.00 max cw p in (dbm) frequency (mhz)
6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 4 rev 1 , may 2017 idtf 1912 n cg i datasheet f1912 s pecification specifications apply at v dd = + 3.3 v, t c ase = +25 c, f rf = 2000 mhz , p in = 0 dbm, serial mode (v mode > v i h ) , z source = z load = 50 ? unless otherwise noted. evkit losses are de - embedded . parameter symbol conditions min typ max units logic input high v ih all control pins v dd > 3.9 v 1.17 3.6 v 3.0 v dd 3.9 v 1.17 v dd - 0.3 v logic input low v il all control pins 0. 63 v logic current i ih, i il all control pins - 35 +35 a supply current i dd v dd = 3.3 v 550 830 1 a v dd = 5.0 v 620 900 rf1 return loss s 11 18 db rf2 return loss s 22 18 db attenuation step lsb least significant bit 0.5 db insertion loss ( minimum attenuation ) a min d[5:0]=[000000] (il state) 1. 4 2.0 db insertion loss ( maximum attenuation ) a m ax d[5:0]=[111111] =31.5 db 32 2 33.0 db step error dnl 0.10 db absolute error inl d[5:0]=[100111]= 19.5 db - 0.7 +0.5 db insertion phase delta at 2 ghz 27 degrees at 4 ghz 55 input ip3 iip3 pin = +10 dbm/tone, tone spacing = 50 mhz attn = 0.0 db, rf in = rf1 60 64.0 dbm attn = 0.0 db, rf in = rf2 56 60.5 attn =15.5 db, rf in = rf1 56 61.0 attn =15.5 db, rf in = rf2 57 61.5 attn = 0.00 db, rf in = rf1 pin = +22 dbm per tone 1 mhz tone separation f rf = 0.7 ghz 60 62.5 f rf = 1.8 ghz 58 61.5 f rf = 2.2 ghz 58 61.0 f rf = 2.6 ghz 57 60.5 input ip 2 iip2 p in = +12dbm/tone, v dd =5.0v f1=945 mhz, f2= 949 mhz f1+f2 = 1894 mhz rf in = rf1 110 dbm 0.1 db compression 3 p 0.1 d[5:0] = [000000] = 0 db 3 1 dbm note 1: items in min/max columns in bold italics are guaranteed by test. note 2: items in min/max columns that are not bold/italics are guaranteed by design characterization . note 3 : the input 0.1db compression point is a linearity figure of merit. refer to absolu te maximum ratings section for the maximum rf input power. note 4: spurious due to on - chip negative voltage generator. typical generator fundamental frequency is 2.2 mhz. note 5 : speeds are measured after spi programming is completed (data latched with le = high) .
6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 5 rev 1 , may 2017 idtf 1912 n cg i datasheet f1912 s pecification ( continued ) specifications apply at v dd = + 3.3 v, t c ase = +25 c, f rf = 2000 mhz , p in = 0 dbm, serial mode (v mode > v i h ) , z source = z load = 50 ? unless otherwise noted. evkit losses are de - embedded . parameter symbol conditions min typ max units msb step time t lsb start le rising edge > v ih end 0.10 db pout settling for 15.5 db to 16.0 db transition 500 n s maximum spurious level on any rf port 4 spur max - 140 dbm maximum switching frequency sw freq 25 k hz dsa settling time ? set max to min attenuation to settle to within 0.5 db of final value 0.9 ? s min to max attenuation to settle to within 0.5 db of final value 1.8 control interface spi bit 6 bit serial clock speed spi clk 25 mhz note 1: items in min/max columns in bold italics are guaranteed by test. note 2: items in min/max columns that are not bold/italics are guaranteed by design characterization . note 3 : the input 0.1db compression point is a linearity figure of merit. refer to absolu te maximum ratings section for the maximum rf input power. note 4: spurious due to on - chip negative voltage generator. typical generator fundamental frequency is 2.2 mhz. note 5: speeds are measured after spi programming is completed (data latched with le = high) .
6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 6 rev 1 , may 2017 idtf 1912 n cg i datasheet p rogramming o ptions f1912 can be programmed using either the parallel or serial interface which is selectable via v mode ( pin 1 3 ) . serial mode is selected by floating v mode or pulling it to a voltage logic high (greater than v ih ) and parallel mode is selected by setting v mode to logic l ow ( less than v il ). s erial c ontrol m ode f 1912 serial mode is selected by floating v mode (pin 1 3) or pulling it to a voltage > v ih . the serial interface is a 6 bit shift register to shift in the dat a msb (d5) first . when serial programming is used, all the parallel control input pins (1, 15, 16, 17, 19, 20) must be grounded. table 1 - 6 bit spi word sequence d5 attenuat ion 16 db control bit d4 attenuator 8 db control bit d3 attenuator 4 db control bit d2 attenuator 2 db control bit d1 attenuator 1 db control bit d0 attenuator 0.5 db control bit table 2 - truth table for serial control word d 5 (msb) d 4 d 3 d 2 d 1 d 0 (lsb) attenuation (db) 0 0 0 0 0 0 0 0 0 0 0 0 1 0.5 0 0 0 0 1 0 1 0 0 0 1 0 0 2 0 0 1 0 0 0 4 0 1 0 0 0 0 8 1 0 0 0 0 0 16 1 1 1 1 1 1 31.5 serial mode r egister t iming d iagram : (note the timing spec intervals in blue ) w ith serial control, the f1912 can be programmed via the serial port on the rising edge of latch en able (le) which loads the last 6 data line bits [formatted msb (d5 ) first] resident in the shift register followed by the next 5 bits .
6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 7 rev 1 , may 2017 idtf 1912 n cg i datasheet figure 2 - serial regist er timing diagram note - when latch enable is high, the shift register is disabled and data is not continuously clocked into the shift register which minimizes noise. it is recommended that latch enable be left high when the device is not being programme d . table 3 - serial mode timing table interval symbol description min spec max spec units t mc parallel to serial setup time - from rising edge of v mode to rising edge of clk for d5 10 0 ns t ds clock high pulse width 10 ns t c ls le setup time - from the rising edge of clk pulse for d0 to le rising edge minus half the clock period. 10 ns t lew le pulse width 30 ns t dsc data setup time - from the starting edge of data bit to rising edge of clk 10 ns t dht data hold tim e - from rising edge of clk to falling edge of the data bit. 10 ns
6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 8 rev 1 , may 2017 idtf 1912 n cg i datasheet serial mode default startup condition: when the device is first powered up it will default to the maximum attenuation of 31.5 db independent of the v mode and parallel pin [d5:d0] conditions. table 4 - default control word for the serial mode d 5 (msb) d 4 d 3 d 2 d 1 d 0 (lsb) attenuation (db) 1 1 1 1 1 1 31.5 p arallel c ontrol m ode for the f1912 the user has the option of running in one of two parallel modes. direct parallel mode or latched parallel mode . direct parallel mode: direct parallel mode is selected when v mode (pin 1 3) is less than v il and le (pin 5 ) is greater than v ih . in this mode the device will immediately react to any voltage changes to the parallel control pins [pins 1, 15, 16, 17, 19, 20 ]. use direct parallel mode for the fastest settling time. latched parallel mode: latched parallel mode is selected when v mode is less than v il and le (pin 5 ) is toggled from less than v il to greater than v ih . to utilize latched parallel mode: ? set le < v il ? adjust pins [ pins 1, 15, 16, 17, 19, 20 ] to the desired attenuation setting. (note the device will not react to these pins w hile le < v il .) ? pull le > v ih . the device will then transition to the attenuation settings reflected by pins d 5 C d0. latched parallel mode implies a default state for when the device is first powered up with vmode < v il and le < v il . in this case the def ault setting is maximum attenuation. table 5 - truth table for the parallel control word d 5 d 4 d 3 d 2 d 1 d 0 attenuation (db) 0 0 0 0 0 0 0 0 0 0 0 0 1 0.5 0 0 0 0 1 0 1 0 0 0 1 0 0 2 0 0 1 0 0 0 4 0 1 0 0 0 0 8 1 0 0 0 0 0 16 1 1 1 1 1 1 31.5
6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 9 rev 1 , may 2017 idtf 1912 n cg i datasheet figure 3 - latched parallel mode timing diagram table 6 - latched parallel mode timing interval symbol description min spec max spec units t sps serial to paralle l mode setup time 100 ns t p dh paralle l data hold time 10 ns t p ds le minimum pulse width 10 ns t le paralle l data setup time 10 ns
6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 10 rev 1 , may 2017 idtf 1912 n cg i datasheet t ypical o perating c onditions (toc) unless otherwise noted for the toc graphs on the following pages , the following conditions apply . ? v dd = + 3 . 3 0 v ? t c ase = +25 c ? f rf = 2 g hz ? p in = 0 dbm for single tone measurements ? p in = +10 dbm/tone for multi - tone measurements ? tone spacing = 50 mhz ? evkit connector and board losses are de - embedded
6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 11 rev 1 , may 2017 idtf 1912 n cg i datasheet t ypical o perating c onditions ( - 1 - ) insertion loss vs frequency rf1 (input) return loss vs frequency [all states] rf2 (output) return loss vs frequency [all states] insertion loss vs attenuation state rf1 (input) return loss vs attenuation state rf2 (output) return loss vs attenuation state - 3.0 - 2.5 - 2.0 - 1.5 - 1.0 - 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 insertion loss (db) frequency (ghz) - 40 c / +3.3 v - 40 c / +5.0 v +25 c / +3.3 v +25 c / +5.0 v +105 c / +3.3 v +105 c / +5.0 v - 30 - 25 - 20 - 15 - 10 - 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 match (db) frequency (ghz) - 30 - 25 - 20 - 15 - 10 - 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 match (db) frequency (ghz) - 35 - 30 - 25 - 20 - 15 - 10 - 5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 insertion loss (db) attenuator state (db) - 40 c / +3.3 v - 40 c / +5.0 v +25 c / +3.3 v +25 c / +5.0 v +105 c / +3.3 v +105 c / +5.0 v - 30 - 25 - 20 - 15 - 10 - 5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 match (db) attenuation (db) 0.5 ghz 1.0 ghz 1.5 ghz 2.0 ghz 2.5 ghz 3.0 ghz 3.5 ghz 4.0 ghz - 30 - 25 - 20 - 15 - 10 - 5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 match (db) attenuation (db) 0.5 ghz 1.0 ghz 1.5 ghz 2.0 ghz 2.5 ghz 3.0 ghz 3.5 ghz 4.0 ghz
6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 12 rev 1 , may 2017 idtf 1912 n cg i datasheet t ypical o perating c onditions ( - 2 - ) relative insertion phase vs frequency worst case absol u te accuracy vs frequency worst case step accuracy vs frequency relative insertion phase vs attenuation absolute accuracy vs attenuation step accuracy vs attenuation - 5 0 5 10 15 20 25 30 35 40 45 50 55 60 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 relative phase (degrees) frequency (ghz) - 1.0 - 0.8 - 0.6 - 0.4 - 0.2 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 error (db) frequency (ghz) - 40 c / min - 40 c / max +25 c / min +25 c / max +105 c / min +105 c / max - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 error (db) frequency (ghz) - 40 c / min - 40 c / max +25 c / min +25 c / max +105 c / min +105 c / max - 5 0 5 10 15 20 25 30 35 40 45 50 55 60 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 phase (degrees) attenuation (db) 0.5 ghz 1.0 ghz 1.5 ghz 2.0 ghz 2.5 ghz 3.0 ghz 3.5 ghz 4.0 ghz - 1.0 - 0.8 - 0.6 - 0.4 - 0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 error (db) attenuation (db) 0.5 ghz 1.0 ghz 1.5 ghz 2.0 ghz 2.5 ghz 3.0 ghz 3.5 ghz 4.0 ghz - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 error (db) attenuation (db) 0.5 ghz 1.0 ghz 1.5 ghz 2.0 ghz 2.5 ghz 3.0 ghz 3.5 ghz 4.0 ghz
6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 13 rev 1 , may 2017 idtf 1912 n cg i datasheet t ypical o perating c onditions ( - 3 - ) compression at 0 db and 2 ghz compression at 15 .5 db and 2 ghz compression at 31 .5 db and 2 ghz inp ut ip3 - 0 db , +22 dbm, 1 mhz tone delta, rf1 in put ip3 (low side) vs attenuation at 2ghz input ip3 (high side) vs attenuation at 2ghz - 0.3 - 0.2 - 0.1 0.0 0.1 0.2 18 20 22 24 26 28 30 32 34 compression (db) input power (dbm) - 40 c +25 c +105 c - 0.3 - 0.2 - 0.1 0.0 0.1 0.2 18 20 22 24 26 28 30 32 34 compression (db) input power (dbm) - 40 c +25 c +105 c - 0.3 - 0.2 - 0.1 0.0 0.1 0.2 18 20 22 24 26 28 30 32 34 compression (db) input power (dbm) - 40 c +25 c +105 c 40 45 50 55 60 65 70 75 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 input ip3 (dbm) frequency (ghz) iip3 - ls iip3 - hs 40 45 50 55 60 65 70 75 80 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 input ip3 (dbm) attenuation (db) - 40 c / pin = 10 dbm/tone - 40 c / pin = 15 dbm/tone +25 c / pin = 10 dbm/tone +25 c / pin = 15 dbm/tone +105 c / pin = 10 dbm/tone +105 c / pin = 15 dbm/tone 40 45 50 55 60 65 70 75 80 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 input ip3 (dbm) attenuation (db) - 40 c / pin = 10 dbm/tone - 40 c / pin = 15 dbm/tone +25 c / pin = 10 dbm/tone +25 c / pin = 15 dbm/tone +105 c / pin = 10 dbm/tone +105 c / pin = 15 dbm/tone
6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 14 rev 1 , may 2017 idtf 1912 n cg i datasheet p ackage d rawing ( 4 mm x 4 mm 20 - pin tqfn), ncg20
6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 15 rev 1 , may 2017 idtf 1912 n cg i datasheet l and p attern d imension
6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 16 rev 1 , may 2017 idtf 1912 n cg i datasheet p in d iagram clk data d 0 d 1 d 3 g n d v mode gnd d 4 le gnd * rf 2 * rf 1 d 2 d 5 v d d n c g n d 2 1 3 5 4 12 11 13 15 14 6 7 9 8 10 16 17 19 18 20 n c n c exposed pad top view ( looking through the top of the package ) * device is rf bi - directional
6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 17 rev 1 , may 2017 idtf 1912 n cg i datasheet p in d escription pin name function 1 d5 16 db attenuation control bit. pull high for 16 db attn. 2 rf1 device rf input or output (bi - directional). internally dc blocked. 3 data serial interface data input. 4 clk serial interface clock input. 5 le serial interface latch enable input. internal pullup (100k ohm). 6 vdd power supply pin. 7 nc internally unconnected. 8 nc internally unconnected. 9 nc internally unconnected. 10 gnd connect to ground. this pin is internally connected to the exposed paddle. 11 gnd connect to ground. this pin is internally connected to the exposed paddle. 12 gnd connect to ground. thi s pin is internally unconnected. 13 v mode pull high for serial control mode. ground for parallel control mode. 14 rf2 device rf input or output (bi - directional). internally dc blocked. 15 d4 8 db attenuation control bit. pull high for 8 db attn. 16 d3 4 db attenuation control bit. pull high for 4 db attn. 17 d2 2 db attenuation control bit. pull high for 2 db attn. 18 gnd connect to ground. this pin is internally unconnected . 19 d1 1 db attenuation control bit. pull high for 1 db attn. 20 d0 0.5 db attenuation control bit. pull high for 0.5 db attn. ep exposed paddle exposed pad. internally connected to gnd. solder this exposed pad to a pcb pad that uses multiple ground vias to provide heat transfer out of the device into the pcb ground p lanes. these multiple via grounds are also required to achieve the specified rf performance.
6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 18 rev 1 , may 2017 idtf 1912 n cg i datasheet e v k it p icture
6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 19 rev 1 , may 2017 idtf 1912 n cg i datasheet ev kit / a pplications c ircuit
6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 20 rev 1 , may 2017 idtf 1912 n cg i datasheet evk it bom item # part reference qty description mfr. part # mfr. 1 c1, c11 2 100nf 10%, 50v, x7r ceramic capacitor (0402) grm155r71h104k murata 2 c2, c12 2 10nf 5%, 50v, c0g ceramic capacitor (0402) grm155r71h103j murata 3 r12, c13, c14 3 0 resistors (0402) erj - 2ge0r00x panasonic 4 r1 - r7 7 100 1%, 1/10w, resistor (0402) erj - 2rkf1000x panasonic 5 r9, r10, r11 3 3k 1%, 1/10w, resistor (0402) erj - 2rkf3001x panasonic 6 r8, r15, r16, r17 4 10k 1%, 1/10w, resistor (0402) erj - 2rkf1002x panasonic 7 r13 1 100k 1%, 1/10w, resistor (0402) erj - 2rkf1003x panasonic 8 r14 1 267k 1%, 1/10w, resistor (0402) erj - 2rkf2673x panasonic 9 j5, j7 2 conn header vert sgl 2 x 1 pos gold 961102 - 6404 - ar 3m 10 j8 1 conn header vert sgl 4 x 1 pos gold 961104 - 6404 - ar 3m 11 j6 1 conn header vert sgl 8 x 1 pos gold 961108 - 6404 - ar 3m 12 j2, j3, j4 3 edge launch sma (0.250 inch pitch ground, round) 142 - 0711 - 821 emerson johnson 13 u1 1 switch 8 position dip switch kat1108e e - switch 14 u2 1 dsa f1912z idt 15 1 printed circuit board (rev 01) f1953s evkit rev 01 idt 16 bill of material (rev 01) t op m arkings i d t f 1 9 1 2 n c g i z 5 1 5 g p a r t n u m b e r d a t e c o d e [ y w w ] ( w e e k 5 o f 2 0 1 5 ) a s m t e s t s t e p a s s e m b l e r c o d e
6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 21 rev 1 , may 2017 idtf 1912 n cg i datasheet a pplications i nformation f1912 digital pin voltage & resistance values (pins not connected) the following table list s the resistance between various pins and ground when no dc power is applied. when the device is powered up with +5 volts dc these same pins to should have the measured voltage to ground. pin name dc voltage (volts) resistance (ohms) 13 v mode 2.5v 100 k? pullup resistor to internally regulated 2.5 v 3, 4, 5 data , clk, le 2.5v 100 k? pullup resistor to internally regulated 2.5 v
6 bit digital step attenuator 1 mhz to 4000 mhz glitch - free tm , digital step attenuator 22 rev 1 , may 2017 idtf 1912 n cg i datasheet revision history revision revision date description of change 1 2017 - may - 26 corrected pin label on page 1 6 . o 2015 - june - 0 6 initial r elease of the datasheet corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1 - 800 - 345 - 7015 or 408 - 284 - 8200 fax: 408 - 284 - 2775 www.idt.com/go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) and its affiliated companies (herein referred to as idt) reserve the right to modify the products and/or specifications described herein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are d etermined in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of a ny kind, whether express or implied, including, but not limited to, the suitability of idt's produc ts for any particular purpose, an implied warranty of merchantability, or non - infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt o r any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an idt product can be reasonably expected to signific antly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the united states and other countries. other trademarks used herein are the property of idt or their respective third party owners. fo r datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . all contents of this document are copyright of integrated device technology, inc. all rights reserved.

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